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quad-channel, digital isolators, enhanced system-level esd reliability data sheet ADUM3400/adum3401/adum3402 rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2006C2012 analog devices, inc. all rights reserved. features enhanced system-level esd performance per iec 61000-4-x low power operation 5 v operation 1.4 ma per channel maximum @ 0 mbps to 2 mbps 4.3 ma per channel maximum @ 10 mbps 34 ma per channel maximum @ 90 mbps 3 v operation 0.9 ma per channel maximum @ 0 mbps to 2 mbps 2.4 ma per channel maximum @ 10 mbps 20 ma per channel maximum @ 90 mbps bidirectional communication 3 v/5 v level translation high temperature operation: 105c high data rate: dc to 90 mbps (nrz) precise timing characteristics 2 ns maximum pulse width distortion 2 ns maximum channel-to-channel matching high common-mode transient immunity: >25 kv/s output enable function 16-lead soic wide body, rohs-compliant package safety and regulatory approvals ul recognition: 2500 v rms for 1 minute per ul 1577 csa component acceptance notice #5a vde certificate of conformity din v vde v 0884-10 (vde v 0884-10): 2006-12 v iorm = 560 v peak applications general-purpose multichannel isolation spi/data converter isolation rs-232/rs-422/rs-485 transceivers industrial field bus isolation general description the adum340x 1 are 4-channel digital isolators based on the analog devices, inc., i coupler? technology. combining high speed cmos and monolithic air core transformer technology, these isolation components provide outstanding performance characteristics superior to alternatives such as optocoupler devices. i coupler devices remove the design difficulties commonly associated with optocouplers. typical optocoupler concerns regarding uncertain current transfer ratios, nonlinear transfer functions, and temperature and lifetime effects are eliminated with the simple i coupler digital interfaces and stable performance characteristics. the need for external drivers and other discrete components is eliminated with these i coupler products. further- more, i coupler devices consume one-tenth to one-sixth the power of optocouplers at comparable signal data rates. the adum340x isolators provide four independent isolation channels in a variety of channel configurations and data rates (see the ordering guide). all models operate with the supply voltage on either side ranging from 2.7 v to 5.5 v, providing compatibility with lower voltage systems as well as enabling a voltage translation functionality across the isolation barrier. the adum340x isolators have a patented refresh feature that ensures dc correctness in the absence of input logic transitions and during power-up/power-down conditions. in comparison to the adum140x isolators, the adum340x isolators contain various circuit and layout changes to provide increased capability relative to system-level iec 61000-4-x testing (esd/burst/surge). the precise capability in these tests for either the adum140x or adum340x products is strongly determined by the design and layout of the users board or module. for more information, see the an-793 application note , esd/latch-up considerations with icoupler isolation products . 1 protected by u.s. patents 5,952,849; 6,873,065; and 7,075,329. functional block diagrams encode decode encode decode encode decode encode decode v dd1 gnd 1 v ia v ib v ic v id nc gnd 1 v dd2 gnd 2 v oa v ob v oc v od v e2 gnd 2 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 05985-001 figure 1. ADUM3400 functional block diagram decode encode encode decode encode decode encode decode v dd1 gnd 1 v ia v ib v ic v od v e1 gnd 1 v dd2 gnd 2 v oa v ob v oc v id v e2 gnd 2 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 05985-002 figure 2. adum3401 functional block diagram decode encode decode encode encode decode encode decode v dd1 gnd 1 v ia v ib v oc v od v e1 gnd 1 v dd2 gnd 2 v oa v ob v ic v id v e2 gnd 2 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 05985-003 figure 3. adum3402 functional block diagram
ADUM3400/adum3401/adum3402 data sheet rev. b | page 2 of 24 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 gene ral description ......................................................................... 1 functional block diagrams ............................................................. 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 electrical characteristics 5 v operation ................................ 3 electrical characteristics 3 v operation ................................ 6 electrical characteristics mixed 5 v/3 v or 3 v/5 v operation ....................................................................................... 8 package characteristics ............................................................. 12 regulatory information ............................................................. 12 insulation and safety - related specifications .......................... 12 din v vde v 0884 - 10 (vde v 0884 - 10) insulation char acteristics ............................................................................ 13 recommended operating conditions .................................... 13 absolute maximum ratings ......................................................... 14 esd caution ................................................................................ 14 pin configurations and function descriptions ......................... 15 typical performance characteristics ........................................... 18 application information ................................................................ 20 pc board layout ........................................................................ 20 system - level esd consideratio ns and enhancements ........ 20 propagation delay - related parameters ................................... 20 dc correctness and magnetic field immunity ........................... 20 power consumption .................................................................. 21 insulation lifetime ..................................................................... 22 outline dimensions ....................................................................... 23 ordering guide .......................................................................... 23 revision history 2/12 rev. a to rev. b created hyperlink for safety and regulatory approvals entry in features section ................................................................. 1 change to pc board layout section ............................................ 20 6 /07 rev. 0 to rev. a updated vde certification throughout ...................................... 1 changes to features, general description, note 1 , figure 1, figure 2, and figure 3 ....................................................................... 1 changes to regulatory information section .............................. 12 changes to table 7 and figure 4 caption .................................... 13 added table 10 ; r enumbered sequentially ................................ 14 added insulation lifetime section .............................................. 22 inserted figure 21, figure 22, and figure 23 .............................. 22 changes to ordering guide .......................................................... 23 3/06 r evision 0: initial version
data sheet ADUM3400/adum3401/adum3402 rev. b | page 3 of 24 specifications electrical character istics 5 v operation all voltages ar e relative to their respective ground. 4.5 v v dd1 5.5 v, 4.5 v v dd2 5.5 v; all min imum /max imum specifications apply over the entire recommended operation range, unless othe r wise noted; all typical specifications are at t a = 25c, v dd1 = v dd2 = 5 v. table 1 . parameter symbol min typ max unit test conditions dc specifications input supply current per channel, quiescent i ddi (q) 0.57 0.83 ma output supply current per channel, quiescent i ddo (q) 0.29 0. 35 ma ADUM3400, total supply current, four channels 1 dc to 2 mbps v dd1 supply current i dd1 (q) 2.9 3. 5 ma dc to 1 mhz logic signal freq. v dd2 supply current i dd2 (q) 1.2 1. 9 ma dc to 1 mhz logic signal freq. 10 mbps (brw and crw grades only) v dd1 supply current i dd1 (10) 9.0 1 1.6 ma 5 mhz logic signal freq. v dd2 supply current i dd2 (10) 3.0 5.5 ma 5 mhz logic signal freq. 90 mbps (crw grade only) v dd1 supply current i dd1 (90) 72 100 ma 45 mhz logic signal freq. v dd2 supply current i dd2 (90) 19 36 ma 45 mhz logic signal fr eq. adum3401, total supply current, four channels 1 dc to 2 mbps v dd1 supply current i dd1 (q) 2.5 3. 2 ma dc to 1 mhz logic signal freq. v dd2 supply current i dd2 (q) 1.6 2. 4 ma dc to 1 mhz logic signal freq. 10 mbps (brw and crw grades only) v dd1 supply current i dd1 (10) 7.4 10.6 ma 5 mhz logic signal freq. v dd2 supply current i dd2 (10) 4.4 6.5 ma 5 mhz logic signal freq. 90 mbps (crw grade only) v dd1 supply current i dd1 (90) 59 82 ma 45 mh z logic signal freq. v dd2 supply current i dd2 (90) 32 46 ma 45 mhz logic signal freq. adum3402, total supply current, four channels 1 dc to 2 mbps v dd1 or v dd2 supply current i dd1 (q) , i dd2 (q) 2.0 2. 8 ma dc to 1 mhz logic signal freq. 10 mbps (brw and crw grades only) v dd1 or v dd2 supply current i dd1 (10) , i dd2 (10) 6.0 7. 5 ma 5 mhz logic signal freq. 90 mbps (crw grade only) v dd1 or v dd2 supply current i dd1 (90) , i dd2 (90) 51 62 ma 45 mhz logic signal freq. for all models input currents i ia , i ib , i ic , i id , i e1 , i e2 ?10 +0.01 +10 a 0 v v ia , v ib , v ic , v id v dd1 or v dd2 , 0 v v e1 , v e2 v dd1 or v dd2 logic high input threshold v ih , v eh 2.0 v logic low input threshold v il , v el 0.8 v logic high output voltages v oah , v obh , (v dd1 or v dd2 ) ? 0.1 5.0 v i ox = ?2 0 a, v ix = v ixh v och , v odh (v dd1 or v dd2 ) ? 0.4 4.8 v i ox = ?4 ma, v ix = v ixh logic low output voltages v oal , v obl , 0.0 0.1 v i ox = 20 a, v ix = v ixl v ocl , v odl 0.04 0.1 v i ox = 400 a, v ix = v ixl 0.2 0.4 v i ox = 4 ma, v ix = v ixl
ADUM3400/adum3401/adum3402 data sheet rev. b | page 4 of 24 parameter symbol min typ max unit test conditions switching s pecifications adum340xarw minimum pulse width 2 pw 1000 ns c l = 15 pf, cmos signal levels maximum data rate 3 1 mbps c l = 15 pf, cmos signal levels propagation delay 4 t phl , t plh 50 65 100 ns c l = 15 pf, cmos signal levels pulse width di stortion , |t plh ? t phl | 4 pwd 40 ns c l = 15 pf, cmos signal levels propagation delay skew 5 t psk 50 ns c l = 15 pf, cmos signal levels channel - to - channel matching 6 t pskcd/od 50 ns c l = 15 pf, cmos signal levels adum340xbrw mini mum pulse width 2 pw 100 ns c l = 15 pf, cmos signal levels maximum data rate 3 10 mbps c l = 15 pf, cmos signal levels propagation delay 4 t phl , t plh 20 32 50 ns c l = 15 pf, cmos signal levels pulse width distortion , |t plh ? t phl | 4 pwd 3 ns c l = 15 pf, cmos signal levels change vs. temperature 5 ps/c c l = 15 pf, cmos signal levels propagation delay skew 5 t psk 15 ns c l = 15 pf, cmos signal levels chann el - to - channel matching, codirectional channels 6 t pskcd 3 ns c l = 15 pf, cmos signal levels channel - to - channel matching, opposing - directional channels 6 t pskod 6 ns c l = 15 pf, cmos signa l levels adum340xcrw minimum pulse width 2 pw 8.3 11.1 ns c l = 15 pf, cmos signal levels maximum data rate 3 90 120 mbps c l = 15 pf, cmos signal levels propagation delay 4 t phl , t plh 18 27 32 ns c l = 15 pf, cmos signal levels pulse width distortion , |t plh ? t phl | 4 pwd 0.5 2 ns c l = 15 pf, cmos signal levels change vs. temperature 3 ps/c c l = 15 pf, cmos signal leve ls propagation delay skew 5 t psk 10 ns c l = 15 pf, cmos signal levels channel - to - channel matching, codirectional channels 6 t pskcd 2 ns c l = 15 pf, cmos signal levels channel - to - channel m atching, opposing - directional channels 6 t pskod 5 ns c l = 15 pf, cmos signal levels for all models output disable propagation delay (high/low -to - high impedance) t phz , t plh 6 8 ns c l = 15 pf, cmos signal levels ou tput enable propagation delay (high impedance -to - high/low) t pzh , t pzl 6 8 ns c l = 15 pf, cmos signal levels output rise/fall time (10% to 90%) t r /t f 2.5 ns c l = 15 pf, cmos signal levels common - mode transient immunity at logic high output 7 |cm h | 25 35 kv/s v ix = v dd1 /v dd2 , v cm = 1000 v, transient magnitude = 800 v common - mode transient immunity at logic low output 7 |cm l | 25 35 kv/s v ix = 0 v, v cm = 1000 v, transient magnitude = 800 v refresh rate f r 1.2 mbps input dynamic supply current per channel 8 i ddi (d) 0.20 ma/mbps output dynamic supply current per channel 8 i ddo (d) 0.05 ma/mbps
data sheet ADUM3400/adum3401/adum3402 rev. b | page 5 of 24 1 the supply current values for all four channels are combined when running at identical data rates. output supply current valu es are specified with no output load present. the supply current associated with an individual channel operating at a given data rate can be calculated as describ ed in the power consumption section. see figur e 8 through figure 10 for information on per - channel supply current as a function of data rate for unloaded and loaded conditions. see figure 11 through figure 15 for total v dd1 a nd v dd2 supply currents as a function of data rate for ADUM3400/adum3401/adum3402 channel configurations. 2 the minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed. 3 the maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed. 4 t phl propagation delay is measured from the 50% level of the falling edge of the v ix signal to the 50% level of the falling edge of the v ox signal. t plh propagation delay is measu red from the 50% level of the rising edge of the v ix signal to the 50% level of the rising edge of the v ox signal. 5 t psk is the magnitude of the worst - case difference in t phl or t plh that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. 6 codirectional channel - to - channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the sa me side of the isolation barrier . opposing - directional channel - to - channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier. 7 cm h is the maximum common - mode voltage slew rate that can be sustained while maintaining v o > 0.8 v dd2 . cm l is the maximum common - mode voltage slew rate that can be sustained while maintaining v o < 0.8 v. the common - mode voltage slew rates apply to both rising and falling common - mode voltage edges. the tra n sient ma gnitude is the range over which the common mode is slewed. 8 dynamic supply current is the incremental amount of supply current required for a 1 mbps increase in signal data rate. see figure 8 through figure 10 for information on per - channel supply current for unloaded and loaded conditions. see the power consumption section for guidance on calculating the per - channel su p ply current for a given data rate.
ADUM3400/adum3401/adum3402 data sheet rev. b | page 6 of 24 electrical character istics 3 v operation all voltages are relative to their respective ground. 2.7 v v dd1 3.6 v, 2.7 v v dd2 3.6 v; all minimum/maximum specifications apply over the entire recommended operation range, unless othe r wise noted; all typical specifications are at t a = 25c, v dd1 = v dd2 = 3.0 v. table 2. parameter symbol min typ max unit test conditions dc specifications input supply current per channel, quiescent i ddi (q) 0.31 0.49 ma output supply current per channel, quiescent i ddo (q) 0.19 0.27 ma ADUM3400, total supply current, four channel s 1 dc to 2 mbps v dd1 supply current i dd1 (q) 1.6 2.1 ma dc to 1 mhz logic signal freq. v dd2 supply current i dd2 (q) 0.7 1. 2 ma dc to 1 mhz logic signal freq. 10 mbps (brw and crw grades only) v dd1 supply current i dd1 (10) 4.8 7.1 ma 5 mhz logic signal freq. v dd2 supply current i dd2 (10) 1.8 2.3 ma 5 mhz logic signal freq. 90 mbps (crw grade only) v dd1 supply current i dd1 (90) 37 54 ma 45 mhz logic signal freq. v dd2 supply current i dd2 (90) 11 15 ma 45 mhz logic signal freq. adum3401, total supply current, four channels 1 dc to 2 mbps v dd1 supply current i dd1 (q) 1.4 1.9 ma dc to 1 mhz logic signal freq. v dd2 supply current i dd2 (q) 0.9 1. 5 ma dc to 1 mhz logic signal freq . 10 mbps (brw and crw grades only) v dd1 supply current i dd1 (10) 4.1 5.6 ma 5 mhz logic signal freq. v dd2 supply current i dd2 (10) 2.5 3.3 ma 5 mhz logic signal freq. 90 mbps (crw grade only) v dd1 supply current i dd1 (90) 31 44 ma 45 m hz logic signal freq. v dd2 supply current i dd2 (90) 17 24 ma 45 mhz logic signal freq. adum3402, total supply current, four channels 1 dc to 2 mbps v dd1 or v dd2 supply current i dd1 (q) , i dd2 (q) 1.2 1. 7 ma d c to 1 mhz logic signal freq. 10 mbps (brw and crw grades only) v dd1 or v dd2 supply current i dd1 (10) , i dd2 (10) 3.3 4.4 ma 5 mhz logic signal freq. 90 mbps (crw grade only) v dd1 or v dd2 supply current i dd1 (90) , i dd2 (90) 24 39 ma 45 mhz logic signal freq. for all models input currents i ia , i ib , i ic , i id , i e1 , i e2 ?10 +0.01 +10 a 0 v v ia , v ib , v ic , v id v dd1 or v dd2 , 0 v v e1 , v e2 v dd1 or v dd2 logic high input threshold v ih , v eh 1.6 v logic low input threshold v il , v el 0.4 v logic high output voltages v oah , v obh , (v dd1 or v dd2 ) ? 0.1 3.0 v i ox = ?20 a, v ix = v ixh v och , v odh (v dd1 or v dd2 ) ? 0.4 2.8 v i ox = ?4 ma, v ix = v ixh logic low output voltages v oal , v obl , 0.0 0.1 v i ox = 20 a, v ix = v ixl v ocl , v odl 0.04 0.1 v i ox = 400 a, v ix = v ixl 0.2 0.4 v i ox = 4 ma, v ix = v ixl switching spe cifications adum340xarw minimum pulse width 2 pw 1000 ns c l = 15 pf, cmos signal levels maximum data rate 3 1 mbps c l = 15 pf, cmos signal levels propagation delay 4 t phl , t plh 50 75 100 ns c l = 15 pf, cmos signal levels
data sheet ADUM3400/adum3401/adum3402 rev. b | page 7 of 24 parameter symbol min typ max unit test conditions pulse width dist ortion , |t plh ? t phl | 4 pwd 40 ns c l = 15 pf, cmos signal levels propagation delay skew 5 t psk 50 ns c l = 15 pf, cmos signal levels channel - to - channel matching 6 t pskcd/od 50 ns c l = 15 pf, cmos signal levels adum340xbrw mini mum pulse width 2 pw 100 ns c l = 15 pf, cmos signal levels maximum data rate 3 10 mbps c l = 15 pf, cmos signal levels propagation delay 4 t phl , t plh 20 38 50 ns c l = 15 pf, cmos signal levels pulse width distortion , |t plh ? t phl | 4 pwd 3 ns c l = 15 pf, cmos signal levels change vs. temperature 5 ps/c c l = 15 pf, cmos signal levels propagation delay skew 5 t psk 22 ns c l = 15 pf, cmos signal levels chann el - to - channel matching, codirectional channels 6 t pskcd 3 ns c l = 15 pf, cmos signal levels channel - to - channel matching, opposing - directional channels 6 t pskod 6 ns c l = 15 pf, cmos signa l levels adum340xcrw minimum pulse width 2 pw 8.3 11.1 ns c l = 15 pf, cmos signal levels maximum data rate 3 90 120 mbps c l = 15 pf, cmos signal levels propagation delay 4 t phl , t plh 20 34 45 ns c l = 15 pf, cmos signal levels pulse width distortion , |t plh ? t phl | 4 pwd 0.5 2 ns c l = 15 pf, cmos signal levels change vs. temperature 3 ps/c c l = 15 pf, cmos signal leve ls propagation delay skew 5 t psk 16 ns c l = 15 pf, cmos signal levels channel - to - channel matching, codirectional channels 6 t pskcd 2 ns c l = 15 pf, cmos signal levels channel - to - channel matching, opposing - directional channels 6 t pskod 5 ns c l = 15 pf, cmos signal levels for all models output disable propagation delay (high/low -to - high impedance) t phz , t plh 6 8 ns c l = 15 pf, cmos signal levels o utput enable propagation delay (high impedance -to - high/low) t pzh , t pzl 6 8 ns c l = 15 pf, cmos signal levels output rise/fall time (10% to 90%) t r /t f 3 ns c l = 15 pf, cmos signal levels common - mode transient immunity at logic high output 7 |cm h | 25 35 kv/s v ix = v dd1 /v dd2 , v cm = 1000 v, transient magnitude = 800 v common - mode transient immunity at logic low output 7 |cm l | 25 35 kv/s v ix = 0 v, v cm = 1000 v, transient magnitude = 800 v refresh rate f r 1.1 mbps input dynamic supply current per channel 8 i ddi (d) 0.10 ma/mbps output dynamic supply current per channel 8 i ddo (d) 0.03 ma/mbps 1 the supply current values for all four channels are combined when running at identical data rates. output supply current values are specified with no o utput load pr e sent. the supply current associated with an individual channel operating at a given data rate can be calculated as de scribed in the power consumption section. see figure 8 through figure 10 for information on per - channel supply current as a function of data rate for unloaded and lo aded conditions. see figure 11 through figure 15 for total v dd1 and v dd2 supply currents as a function of data rate for ADUM3400/adum3401/adum3402 channel configurations. 2 the minimum pulse width is the s hortest pulse width at which the specified pulse width distortion is guaranteed. 3 the maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed. 4 t phl propagation delay is measured from the 50% level of the fa lling edge of the v ix signal to the 50% level of the falling edge of the v ox signal. t plh propagation delay is measured from the 50% level of the rising edge of the v ix signal to the 50% level of the rising edge of the v ox signal. 5 t psk is the magnitude o f the worst - case difference in t phl or t plh that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. 6 codirectional channel - to - channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. opposing - directional channel - to - channel matching is the absolute value of the difference in propagation delays between any two channels wi th inputs on opposing sides of the isolation barrier. 7 cm h is the maximum common - mode voltage slew rate that can be sustained while maintaining v o > 0.8 v dd2 . cm l is the maximum common - mode voltage slew rate that can be sustained while maintaining v o < 0. 8 v. the common - mode voltage slew rates apply to both rising and falling common - mode voltage edges. the tra n sient magnitude is the range over which the common mode is slewed. 8 dynamic supply current is the incremental amount of supply current required for a 1 mbps increase in signal data rate. see figure 8 through figure 10 for information on per - channel supply current for unloaded and loaded conditions. see the power consumption se ction for guidance on calculating the per - channel su p ply current for a given data rate.
ADUM3400/adum3401/adum3402 data sheet rev. b | page 8 of 24 electrical character istics mixed 5 v/3 v or 3 v /5 v operation all vol tages are relative to their respective ground. 5 v/3 v operation : 4.5 v v dd1 5.5 v, 2.7 v v dd2 3.6 v; 3 v/5 v operation: 2.7 v v dd1 3.6 v, 4.5 v v dd2 5.5 v; all minimum/maximum specifications apply over the entire recommended operation range, unless otherwise noted; all typical specifications are at t a = 25c; v dd1 = 3.0 v, v dd2 = 5 v or v dd1 = 5 v, v dd2 = 3.0 v. table 3 . parameter symbol min typ max unit test conditions dc specifications input supply current per channel, quie s cent i ddi (q) 5 v/3 v operation 0.57 0.83 ma 3 v/5 v operation 0.31 0.49 ma output supply current per channel, quiescent i ddo (q) 5 v/3 v operation 0.29 0.27 ma 3 v/5 v operation 0.19 0.35 ma ADUM3400, total supply current, four channels 1 dc to 2 mbps v dd1 s upply current i dd1 (q) 5 v/3 v operation 2.9 3. 5 ma dc to 1 mhz logic si g nal freq. 3 v/5 v operation 1.6 2.1 ma dc to 1 mhz logic si g nal freq. v dd2 supply current i dd2 (q) 5 v/3 v operation 0.7 1. 2 ma dc to 1 mhz logic si g nal freq. 3 v /5 v operation 1.2 1. 9 ma dc to 1 mhz logic si g nal freq. 10 mbps (brw and crw grades only) v dd1 supply current i dd1 (10) 5 v/3 v operation 9.0 1 1.6 ma 5 mhz logic signal freq. 3 v/5 v operation 4.8 7.1 ma 5 mhz logic signal freq. v dd2 supply current i dd2 (10) 5 v/3 v operation 1.8 2.3 ma 5 mhz logic signal freq. 3 v/5 v operation 3.0 5.5 ma 5 mhz logic signal freq. 90 mbps (crw grade only) v dd1 supply current i dd1 (90) 5 v/3 v operation 72 100 ma 45 mhz logic signal freq. 3 v/5 v operation 37 54 ma 45 mhz logic signal freq. v dd2 supply current i dd2 (90) 5 v/3 v operation 11 15 ma 45 mhz logic signal freq. 3 v/5 v operation 19 36 ma 45 mhz logic signal freq. adum3401, total supply current, four channels 1 dc to 2 mbps v dd1 supply current i dd1 (q) 5 v/3 v operation 2.5 3. 2 ma dc to 1 mhz logic si g nal freq. 3 v/5 v operation 1.4 1.9 ma dc to 1 mhz logic si g nal freq. v dd2 supply current i dd2 ( q) 5 v/3 v operation 0.9 1. 5 ma dc to 1 mhz logic si g nal freq. 3 v/5 v operation 1.6 2. 4 ma dc to 1 mhz logic si g nal freq. 10 mbps (brw and crw grades only) v dd1 supply current i dd1 (10) 5 v/3 v operation 7.4 10.6 ma 5 mhz logic signal freq. 3 v/5 v operation 4.1 5.6 ma 5 mhz logic signal freq. v dd2 supply current i dd2 (10) 5 v/3 v operation 2.5 3.3 ma 5 mhz logic signal freq. 3 v/5 v operation 4.4 6.5 ma 5 mhz logic signal freq.
data sheet ADUM3400/adum3401/adum3402 rev. b | page 9 of 24 parameter symbol min typ max unit test conditions 90 mbps (crw grade only) v dd1 supply current i dd1 (90) 5 v/3 v operation 59 82 ma 45 mhz logic signal freq. 3 v/5 v operation 31 44 ma 45 mhz logic signal freq. v dd2 supply current i dd2 (90) 5 v/3 v operation 17 24 ma 45 mhz logic signal freq. 3 v/5 v operation 32 46 ma 45 mhz logic signal freq. adum3402, total supply current, four channels 1 dc to 2 mbps v dd1 supply current i dd1 (q) 5 v/3 v operation 2.0 2.8 ma dc to 1 mhz logic signal freq. 3 v/5 v operation 1.2 1.7 ma dc to 1 mhz logic signal freq. v dd2 supply current i dd2 (q) 5 v/3 v operation 1.2 1.7 ma dc to 1 mhz logic signal freq. 3 v/5 v operation 2.0 2.8 ma dc to 1 mhz logic signal freq. 10 mbps (brw and crw grades only) v dd1 supply current i dd1 (10) 5 v/3 v operation 6.0 7.5 ma 5 mhz logic signal freq. 3 v/5 v operation 3.3 4.4 ma 5 mhz logic signal freq. v dd2 supply current i dd2 (10) 5 v/3 v operation 3.3 4.4 ma 5 mhz logic signal freq. 3 v/5 v operation 6.0 7.5 ma 5 mhz logic signal freq. 90 mbps (crw grade only) v dd1 supply current i dd1 (90) 5 v/3 v operation 46 62 ma 45 mhz logic signal freq. 3 v/5 v operation 24 39 ma 45 mhz logic signal freq. v dd2 supply current i dd2 (90) 5 v/3 v operation 24 39 ma 45 mhz logic signal freq. 3 v/5 v operation 46 62 ma 45 mhz logic signal freq. for all models input currents i ia , i ib , i ic , i id , i e1 , i e2 ?10 +0.01 +10 a 0 v v ia ,v ib , v ic ,v id v dd1 or v dd2 , 0 v v e1 ,v e2 v dd1 or v dd2 logic high input threshold v ih , v eh 5 v/3 v operation 2.0 v 3 v/5 v operation 1.6 v logic low input threshold v il , v el 5 v/3 v operation 0.8 v 3 v/5 v operation 0.4 v logic high output voltages v oah , v obh , (v dd1 or v dd2 ) ? 0.1 (v dd1 or v dd2 ) v i ox = ?20 a, v ix = v ixh v och , v odh (v dd1 or v dd2 ) ? 0.4 (v dd1 or v dd2 ) ? 0.2 v i ox = ?4 ma, v ix = v ixh logic low output voltages v oal , v obl , 0.0 0.1 v i ox = 20 a, v ix = v ixl v ocl , v odl 0.04 0.1 v i ox = 400 a, v ix = v ixl 0.2 0.4 v i ox = 4 ma, v ix = v ixl switching specifications adum340xarw minimum pulse width 2 pw 1000 ns c l = 15 pf, cmos signal levels maximum data rate 3 1 mbps c l = 15 pf, cmos signal levels propagation delay 4 t phl , t plh 50 70 100 ns c l = 15 pf, cmos signal levels pulse width distortion, |t plh ? t phl | 4 pwd 40 ns c l = 15 pf, cmos signal levels propagation delay skew 5 t psk 50 ns c l = 15 pf, cmos signal levels channel-to-channel matching 6 t pskcd/od 50 ns c l = 15 pf, cmos signal levels
ADUM3400/adum3401/adum3402 data sheet rev. b | page 10 of 24 parameter symbol min typ max unit test conditions adum340xbrw mini mum pulse width 2 pw 100 ns c l = 15 pf, cmos signal levels maximum data rate 3 10 mbps c l = 15 pf, cmos signal levels propagation delay 4 t phl , t plh 15 35 50 ns c l = 15 pf, cmos signal levels pulse width distortion , |t plh ? t phl | 4 pwd 3 ns c l = 15 pf, cmos signal levels change vs. temperature 5 ps/c c l = 15 pf, cmos signal levels propagation delay skew 5 t psk 22 ns c l = 15 pf, cmos signal levels chann el - to - channel matching, codirectional channels 6 t pskcd 3 ns c l = 15 pf, cmos signal levels channel - to - channel matching, oppo s ing - directional channels 6 t pskod 6 ns c l = 15 pf, cmos signa l levels adum340xcrw minimum pulse width 2 pw 8.3 11.1 ns c l = 15 pf, cmos signal levels maximum data rate 3 90 120 mbps c l = 15 pf, cmos signal levels propagation delay 4 t phl , t plh 20 30 40 ns c l = 15 pf, cmos signal levels pulse width distortion , |t plh ? t phl | 4 pwd 0.5 2 ns c l = 15 pf, cmos signal levels change vs. temperature 3 ps/c c l = 15 pf, cmos signal leve ls propagation delay skew 5 t psk 14 ns c l = 15 pf, cmos signal levels channel - to - channel matching, codirectional channels 6 t pskcd 2 ns c l = 15 pf, cmos signal levels channel - to - channel matching, oppo s ing - directional channels 6 t pskod 5 ns c l = 15 pf, cmos signal levels for all models output disable propagation delay (high/low -to - high impedance) t phz , t plh 6 8 ns c l = 15 pf, cmos signal levels o utput enable propagation delay (high impedance -to - high/low) t pzh , t pzl 6 8 ns c l = 15 pf, cmos signal levels output rise/fall time (10% to 90%) t r /t f c l = 15 pf, cmos signal levels 5 v/3 v operation 3.0 ns 3 v/5 v operation 2.5 ns common -m ode transient immunity at logic high output 7 |cm h | 25 35 kv/s v ix = v dd1 /v dd2 , v cm = 1000 v, transient magnitude = 800 v common - mode transient immunity at logic low output 7 |cm l | 25 35 kv/s v ix = 0 v, v cm = 1000 v, tra n sient magnitude = 800 v refresh rate f r 5 v/3 v operation 1.2 mbps 3 v/5 v operation 1.1 mbps input dynamic supply current per channel 8 i ddi (d) 5 v/3 v operation 0.20 ma/mbps 3 v/5 v operation 0.10 ma/mbps output dynam ic supply current per channel 8 i dd o (d) 5 v/3 v operation 0.03 ma/mbps 3 v/5 v operation 0.05 ma/mbps
data sheet ADUM3400/adum3401/adum3402 rev. b | page 11 of 24 1 the supply current values for all four channels are combined when running at identical data rates. output supply current valu es are specified with no output load pres ent. the supply cu r rent associated with an individual channel operating at a given data rate can be calculated as described in the power consumption section. see figure 8 thr ough figure 10 for information on per - channel supply current as a function of data rate for unloaded and loaded conditions. see figure 11 through fig ure 15 for total v dd1 and v dd2 su p ply currents as a function of data rate for ADUM3400/adum340 1/ adum340 2 channel configurations. 2 the minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed. 3 the maxim um data rate is the fastest data rate at which the specified pulse width distortion is guaranteed. 4 t phl propagation delay is measured from the 50% level of the falling edge of the v ix signal to the 50% level of the falling edge of the v ox signal. t plh pr opagation delay is measured from the 50% level of the rising edge of the v ix signal to the 50% level of the rising edge of the v ox signal. 5 t psk is the magnitude of the worst - case difference in t phl or t plh that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. 6 codirectional channel - to - channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the sa me side of the isolation barrier. opposing - directional channel - to - channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier. 7 cm h is the maximum common - mode volta ge slew rate that can be sustained while maintaining v o > 0.8 v dd2 . cm l is the maximum common - mode voltage slew rate that can be sustained while maintaining v o < 0.8 v. the common - mode voltage slew rates apply to both rising and falling common - mode voltage edges. the transient magnitude is the range over which the common mode is slewed. 8 dynamic supply current is the incremental amount of supply current required for a 1 mbps increase in signal data rate. see figure 8 through figure 10 for information on per - channel supply current for unloaded and loaded conditions. see the power consumption section for guidance on calculating the per - ch annel supply current for a given data rate.
ADUM3400/adum3401/adum3402 data sheet rev. b | page 12 of 24 package characterist ics table 4. parameter symbol min typ max unit test conditions resistance (input -to - output) 1 r i - o 10 12 ? capacitance (input -to - output) 1 c i - o 2.2 pf f = 1 mhz input capacitance 2 c i 4.0 pf ic junction - to - case thermal resistance, side 1 jci 33 c/w thermocouple l ocated at center of package underside ic junction - to - case thermal resistance, side 2 jco 28 c/w 1 device considered a 2 - terminal device; pin 1 to pin 8 are shorted together and pin 9 to pin 16 are shorted together. 2 input capacitance is from any input data pin to ground. regulatory informati on the adum340x is approved by the organizations listed in table 5 . refer to table 10 and the insulation lifetime section for details regarding recommended maximum working voltages for specific crossisolation waveforms and insulation levels. table 5. ul csa vde recognized under 1577 component recogn i tion program 1 approved under csa component acce p tance notice #5a certified according to din v vde v 0884 - 10 (vde v 0884 - 10): 2006 - 12 2 double/reinforced ins u lation, 2500 v rms isolation vo lt age basic insulation per csa 60950 -1- 03 and iec 60950 - 1, 800 v rms (1131 v peak) maximum working voltage reinforced insulation, 560 v peak reinforced insulation per csa 60950 -1-03 and iec 60950 -1, 400 v rms (566 v peak) maximum working voltage file e214100 file 205078 file 2471900 - 4880 - 0001 1 in accordance with ul 1577, each adum340x is proof tested by applying an insulation test voltage 3000 v rms for 1 sec (current leakage detection limit = 5 a ). 2 in accordance with din v vde v 0884 - 10 , each adum340x is proof tested by applying an insulation test voltage 1050 v peak for 1 sec (partial discharge detection limit = 5 pc). the * marking branded on the component designates din v vde v 0884 - 10 approval. insulation and safet y- related specificatio ns table 6. parameter symbol value unit conditions rated dielectric insulation voltage 2500 v rms 1- minute duration minimum external air gap (clearance) l(i01) 7.7 min mm measured from input terminals to output terminals, shortest distance through air minimum external tracking (creepage) l(i02) 8.1 min mm measured from input terminals to output terminals, shortest distance path along body m inimum internal gap (internal clearance) 0.017 min mm insulation distance through insulation tracking resistance (comparative tracking index ) cti >175 v din iec 112/vde 0303 part 1 isolation group iiia material group (din vde 0110, 1/89, table 1)
data sheet ADUM3400/adum3401/adum3402 rev. b | page 13 of 24 d in v vde v 0884 - 10 (vde v 0884 - 10) insulation character istics these isolators are suitable for reinforced electrical isolation only within the safety limit data. maintenance of the safety data is ensured by prote c tive circuits. the * marking on packages de notes din v vde v 0884 - 10 approval. table 7. description conditions symbol characteristic unit installation classification per din vde 0110 for rated mains voltage 150 v rms i to iv for rated mains voltage 300 v rms i to iii for rated mains voltage 400 v rms i to ii climatic classification 40/105/21 pollution degree per din vde 0110, table 1 2 maximum working insulation voltage v iorm 560 v peak input - to - output test voltage, method b1 v iorm 1.875 = v pr , 100% production test, t m = 1 sec, partial discharge < 5 pc v pr 1050 v peak input - to - output test voltage, method a v iorm 1.6 = v pr , t m = 60 sec, partial discharge < 5 pc v pr after environmental tests subgroup 1 896 v peak after input and/or safety test subgroup 2 and subgroup 3 v iorm 1.2 = v pr , t m = 60 sec, partial discharge < 5 pc 672 v peak highest allowable overvoltage transient overvoltage, t tr = 10 seconds v tr 4000 v p eak safety - limiting values maximum value allowed in the event of a failure (see figure 4 ) case temperature t s 150 c side 1 current i s1 265 ma side 2 current i s2 335 ma insulation resistance at t s v io = 500 v r s >10 9 ? case temperature (c) safety-limiting current (ma) 0 0 350 300 250 200 150 100 50 50 100 150 200 side #1 side #2 05985-004 figure 4 . thermal derating curve, dependence of safety - limiting values with case temperature per din v vde v 0884 - 10 recommended operating conditions table 8. parameter rating operating temperature range (t a ) ?40c to +105c supply voltages (v dd1 , v dd2 ) 1 2.7 v to 5.5 v input signal rise and fall times 1.0 ms 1 all voltages are relative to their respective ground. see the dc correctness and ma gnetic field imm u nity section for information on immunity to external ma g netic fields.
ADUM3400/adum3401/adum3402 data sheet rev. b | page 14 of 24 absolute maximum rat ings ambient temperature = 25c, unless otherwise noted. table 9. parameter rating storage temperature range (t st ) ?65c to +150c ambient operating temperature range (t a ) ?40c to +105c supply voltages (v dd1 , v dd2 ) 1 ?0.5 v to +7.0 v input voltage ( v ia , v ib , v ic , v id , v e1 , v e2 ) 1 , 2 ?0.5 v to v d d1 + 0.5 v output voltage (v oa , v ob , v oc , v od ) 1 , 2 ?0.5 v to v ddo + 0.5 v average output current per pin 3 side 1 (i o1 ) ?18 ma to +18 ma side 2 (i o2 ) ?22 ma to +22 ma common - mode transi ents (cm h , cm l ) 4 ?100 kv/s to +100 kv/s 1 all voltages are relative to their respective ground. 2 v ddi and v ddo refer to the supply voltages on the input and output sides of a given channel, respectively. see the pc board layout section. 3 see figure 4 for maximum rated current values for various temperatures. 4 refers to common - mode transients across the insulation barrier. common - mode transients exceeding the absolute maximum ratings can cause latch - up or perm a nent damage. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those i ndicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution table 10 . maximum continuous working v oltage 1 parameter max unit constraint ac voltage, bipolar waveform 565 v peak 50- year minimum lifetime ac voltage, unipolar waveform basic insulation 1131 v peak maximum approved working voltage per iec 60950 -1 reinforced insulation 560 v peak maxim um approved working voltage per iec 60950 - 1 and vde v 0884-10 dc voltage basic insulation 1131 v peak maximum approved working voltage per iec 60950 -1 reinforced insulation 560 v peak maximum approved working voltage per iec 60950 - 1 and vde v 0884-10 1 refers to continuous voltage magnitude imposed across the isolation barrier. see the insulation lifetime section for more details. table 11 . truth table (positive logic) v i x input 1 v e x input 2 v ddi state 1 v ddo state 1 v ox output 1 notes h h or nc powered powered h l h or nc powered powered l x l powered powered z x h or nc unpowered powered h outputs return to the input state within 1 s of v ddi power restor a tion. x l unpowered powered z x x powered unpowered indeterminate outputs return to the input state within 1 s of v ddo power restor a tion if v ex state is h or nc. outputs return to high impedance state within 8 ns of v ddo power restoration if v ex state is l. 1 v ix and v ox refer to the input and output signals of a given channel (a, b, c, or d). v ex refers to the output enable signal on the same side as the v ox outputs. v ddi and v ddo refer to the supply voltages on the input and output sides of the given channel, re spectively. 2 in noisy environments, connecting v ex to an external logic high or low is recommended.
data sheet ADUM3400/adum3401/adum3402 rev. b | page 15 of 24 pin configurations and function descript ions v dd1 1 *gnd 1 2 v ia 3 v ib 4 v dd2 16 gnd 2 * 15 v oa 14 v ob 13 v ic 5 v oc 12 v id 6 v od 11 nc 7 v e2 10 *gnd 1 8 gnd 2 * 9 nc = no connect ADUM3400 top view (not to scale) *pin 2 and pin 8 are internally connected and connecting both to gnd 1 is recommended. pin 9 and pin 15 are internally connected and connecting both to gnd 2 is recommended. in noisy environments, connecting output enables (pin 7 for adum3401/adum3402 and pin 10 for all models) to an external logic high or low is recommended. 05985-005 figure 5 . ADUM3400 p in configuration table 12 . ADUM3400 pin function descriptions pin no. mnemonic description 1 v dd1 supply voltage for isolator side 1, 2.7 v to 5.5 v. 2 , 8 gnd 1 ground 1. ground r eference for i solator side 1. 3 v ia logic input a. 4 v ib logic input b. 5 v ic logic input c. 6 v id logic input d. 7 nc no connect. 9 , 15 gnd 2 ground 2. ground reference for i solator side 2. 10 v e2 output enable 2. active high logic input. v oa , v ob , v oc , and v od outputs are enabled when v e2 is high o r disconnected. v oa , v ob , v oc , and v od outputs are disabled when v e2 is low. in noisy environments, connecting v e2 to an external logic high or low is recommended. 11 v od logic output d. 12 v oc logic output c. 13 v ob logic output b. 14 v oa logic outpu t a. 16 v dd2 supply voltage for isolator side 2, 2.7 v to 5.5 v.
ADUM3400/adum3401/adum3402 data sheet rev. b | page 16 of 24 v dd1 1 *gnd 1 2 v ia 3 v ib 4 v dd2 16 gnd 2 * 15 v oa 14 v ob 13 v ic 5 v oc 12 v od 6 v id 11 v e1 7 v e2 10 *gnd 1 8 gnd 2 * 9 adum3401 top view (not to scale) *pin 2 and pin 8 are internally connected and connecting both to gnd 1 is recommended. pin 9 and pin 15 are internally connected and connecting both to gnd 2 is recommended. in noisy environments, connecting output enables (pin 7 for adum3401/adum3402 and pin 10 for all models) to an external logic high or low is recommended. 05985-006 figure 6 . adum3401 pin configuration table 13 . adum3401 pin function descriptions pin no. mnemonic description 1 v dd1 supply voltage for isolator side 1, 2.7 v to 5.5 v. 2 , 8 gnd 1 ground 1. ground reference for i solator side 1. 3 v ia logic input a. 4 v ib logic input b. 5 v ic logic input c. 6 v od logic output d. 7 v e1 output enable 1. active high logic input. v od output is enabled when v e1 is high or disconnected. v od is disabled when v e1 is low. in noisy environments, connecting v e1 to an external logic high or low is recommended. 9 , 15 gnd 2 ground 2. ground reference for i solator side 2. 10 v e2 output enable 2. active high logi c input. v oa , v ob , and v oc outputs are enabled when v e2 is high or disconnected. v oa , v ob , and v oc outputs are disabled when v e2 is low. in noisy environments, connecting v e2 to an external logic high or low is re c ommended. 11 v id logic input d. 12 v oc logic output c. 13 v ob logic output b. 14 v oa logic output a. 16 v dd2 supply voltage for isolator side 1, 2.7 v to 5.5 v.
data sheet ADUM3400/adum3401/adum3402 rev. b | page 17 of 24 v dd1 1 *gnd 1 2 v ia 3 v ib 4 v dd2 16 gnd 2 * 15 v oa 14 v ob 13 v oc 5 v ic 12 v od 6 v id 11 v e1 7 v e2 10 *gnd 1 8 gnd 2 * 9 adum3402 top view (not to scale) *pin 2 and pin 8 are internally connected and connecting both to gnd 1 is recommended. pin 9 and pin 15 are internally connected and connecting both to gnd 2 is recommended. in noisy environments, connecting output enables (pin 7 for adum3401/adum3402 and pin 10 for all models) to an external logic high or low is recommended. 05985-007 figure 7 . adum3402 pin configuration table 14 . adum3402 pin function descr iptions pin no. mnemonic description 1 v dd1 supply voltage for isolator side 1, 2.7 v to 5.5 v. 2 , 8 gnd 1 ground 1. ground reference for i solator side 1. 3 v ia logic input a. 4 v ib logic input b. 5 v oc logic output c. 6 v od logic output d. 7 v e1 out put enable 1. active high logic input. v oc and v od outputs are enabled when v e1 is high or disconnected. v oc and v od outputs are disabled when v e1 is low. in noisy environments, connecting v e1 to an external logic high or low is recommended. 9 , 15 gnd 2 ground 2. ground reference for i solator side 2. 10 v e2 output enable 2. active high logic input. v oa and v ob outputs are enabled when v e2 is high or disconnected. v oa and v ob outputs are disabled when v e2 is low. in noisy environments, connecting v e2 to an external logic high or low is recommended. 11 v id logic input d. 12 v ic logic input c. 13 v ob logic output b. 14 v oa logic output a. 16 v dd2 supply voltage for isolator side 2, 2.7 v to 5.5 v.
ADUM3400/adum3401/adum3402 data sheet rev. b | page 18 of 24 typical performance characteristics data rate (mbps) current/channel (ma) 0 0 20 40 20 60 80 100 5v 3v 15 10 5 05985-008 figure 8 . typical input supply current per channel vs. data rate (no load) data rate (mbps) current/channel (ma) 0 0 20 40 20 60 80 100 5v 3v 15 10 5 05985-009 figure 9 . typical output supply current per channel vs. data rate (no load) data rate (mbps) current/channel (ma) 0 0 20 40 20 60 80 100 5v 3v 15 10 5 05985-010 figure 10 . typical output supply current per channel vs. data rate (15 pf output load) data rate (mbps) current (ma) 0 0 80 40 20 60 80 100 5v 3v 60 40 20 05985-011 figure 11 . typical ADUM3400 v dd1 supply current vs. data rate for 5 v and 3 v operation data rate (mbps) current (ma) 0 0 80 40 20 60 80 100 5v 3v 60 40 20 05985-012 figure 12 . typical ADUM3400 v dd2 supply current vs . data rate for 5 v and 3 v operation data rate (mbps) current (ma) 0 0 80 40 20 60 80 100 5v 3v 60 40 20 05985-013 figure 13 . typical adum3401 v dd1 supply current vs. data rate for 5 v and 3 v operation
data sheet ADUM3400/adum3401/adum3402 rev. b | page 19 of 24 data rate (mbps) current (ma) 0 0 80 40 20 60 80 100 5v 3v 60 40 20 05985-014 figure 14 . typical adum3401 v dd2 supply current vs. data rate for 5 v and 3 v operation data rate (mbps) current (ma) 0 0 80 40 20 60 80 100 5v 3v 60 40 20 05985-015 figure 15 . typical adum3402 v dd1 or v dd2 supply current vs. data rate for 5 v and 3 v operation temperature (c) propagation delay (ns) ?50 ?25 25 30 35 40 0 50 75 25 100 3v 5v 05985-016 figure 16 . propagation delay vs. temperature, c grade
ADUM3400/adum3401/adum3402 data sheet rev. b | page 20 of 24 application information pc board layout the adum340x digital isolator requires no external interface circuitry for the logic interfaces. power supply bypassing is strongly recommended at the input and output supply pins (see figure 17). bypass capacitors are most conveniently connected between pin 1 and pin 2 for v dd1 and between pin 15 and pin 16 for v dd2 . the capacitor value should be between 0.01 f and 0.1 f. the total lead length between both ends of the capacitor and the input power supply pin should not exceed 20 mm. bypassing between pin 1 and pin 8 and between pin 9 and pin 16 should also be considered unless the ground pair on each package side is connected close to the package. v dd1 gnd 1 v ia v ib v ic/oc v id/od v e1 gnd 1 v dd2 gnd 2 v oa v ob v oc/ic v od/id v e2 gnd 2 0 5985-017 figure 17. recommended printed circuit board layout in applications involving high common-mode transients, care should be taken to ensure that board coupling across the isolation barrier is minimized. furthermore, the board layout should be designed such that any coupling that does occur equally affects all pins on a given component side. failure to ensure this could cause voltage differentials between pins exceeding the absolute maximum ratings of the device, thereby leading to latch-up or permanent damage. see the an-1109 application note for board layout guidelines. system-level esd considerations and enhancements system-level esd reliability (for example, per iec 61000-4-x) is highly dependent on system design, which varies widely by application. the adum340x incorporate many enhancements to make esd reliability less dependent on system design. the enhancements include: ? esd protection cells added to all input/output interfaces. ? key metal trace resistances reduced using wider geometry and paralleling of lines with vias. ? the scr effect inherent in cmos devices minimized by use of guarding and isolation technique between pmos and nmos devices. ? areas of high electric field concentration eliminated using 45 corners on metal traces. ? supply pin overvoltage prevented with larger esd clamps between each supply pin and its respective ground. while the adum340x improve system-level esd reliability, they are no substitute for a robust system-level design. see the an-793 application note, esd/latch-up considerations with icoupler isolation products for detailed recommendations on board layout and system-level design. propagation delay-related parameters propagation delay is a parameter that describes the time it takes a logic signal to propagate through a component. the propagation delay to a logic low output can differ from the propagation delay to a logic high. input ( v ix ) output (v ox ) t plh t phl 50% 50% 05985-018 figure 18. propagation delay parameters pulse width distortion is the maximum difference between these two propagation delay values and is an indication of how accurately the input signals timing is preserved. channel-to-channel matching refers to the maximum amount the propagation delay differs between channels within a single adum340x component. propagation delay skew refers to the maximum amount the propagation delay differs between multiple adum340x components operating under the same conditions. dc correctness and magnetic field immunity positive and negative logic transitions at the isolator input cause narrow (~1 ns) pulses to be sent to the decoder via the transformer. the decoder is bistable and is, therefore, either set or reset by the pulses, indicating input logic transitions. in the absence of logic transitions at the input for more than ~1 s, a periodic set of refresh pulses indicative of the correct input state are sent to ensure dc correctness at the output. if the decoder receives no internal pulses of more than about 5 s, the input side is assumed to be unpowered or nonfunctional, in which case the isolator output is forced to a default state (see table 11) by the watchdog timer circuit. the limitation on the magnetic field immunity of the adum340x is set by the condition in which induced voltage in the receiving coil of the transformer is sufficiently large to either falsely set or reset the decoder. the following analysis defines the conditions under which this can occur. the 3 v operating condition of the adum340x is examined because it represents the most susceptible mode of operation.
data sheet ADUM3400/adum3401/adum3402 rev. b | page 21 of 24 the pulses at the transformer output have an amplitude greater than 1.0 v. the decoder has a sensing threshold at about 0.5 v, thus establishing a 0.5 v margin in which induced voltages can be tolerated. the voltage induced across the receiving coil is given by v = ( ?d /dt )? r n 2 ; n = 1, 2, , n where: is magnetic flux density (gauss). n is the number of turns in the receiving coil. r n is the radius of the n th turn in the receiving coil (cm). given the geometry of the receiving coil in the adum340x and an imposed requirement that the induced voltage be at most 50% of the 0.5 v margin at the decoder, a maximum allowable magnetic field is calculated as shown in figure 19 . magnetic field frequency (hz) 100 maximum allowable magnetic flux density (kgauss) 0.001 1m 10 0. 01 1k 10k 10m 0.1 1 100m 100k 05985-019 figure 19 . maximum allowable external magnetic flux density for example, at a magnetic field frequency of 1 mhz, the maximum allowable magnetic field of 0.2 kgauss induces a vol t age of 0.25 v at the receiving coil , which is about 50% of the sen s ing threshold and does not cause a faulty output transition. sim i larly, if such an event were to occur during a transmitted pulse (and was of the worst - case pol arity), it would reduce the re ceived pulse from >1.0 v to 0.75 v still well above the 0.5 v sensing threshold of the decoder. the preceding magnetic flux density values correspond to spe cific current magnitudes at given distances from the adum340x transfor mers. figure 20 expresses these allowable current magnitudes as a function of frequency for selected di s tances. as shown, the adum340x is extremely immune and can be affected only by extremely large currents operate d at high frequency very close to the component. for the 1 mhz example noted, one would have to place a 0.5 ka current 5 mm away from the adum340x to affect the operation of the component . magnetic field frequency (hz) maximum allowable current (ka) 1000 100 10 1 0.1 0.01 1k 10k 100m 100k 1m 10m distance = 5mm distance = 1m distance = 100mm 05985-020 figure 20 . maximum allowable current for various current -to- adum340x spacings note that at combinations of strong magnetic field and high frequency, any loops formed by printed circuit board traces could induce error voltages sufficiently large enough to trigger the thresholds of succeeding circ uitry. care should be taken in the layout of such traces to avoid this possibility. power consumption the supply current at a given channel of the adum340x isol a tor is a function of the supply voltage, the channels data rate, and the channels output load . for each input channel, the supply current is given by i ddi = i ddi ( q ) f 0.5 f r i ddi = i ddi (d) (2 f ? f r ) + i ddi ( q ) f > 0.5 f r for each output channel, the supply current is given by i ddo = i ddo ( q ) f 0.5 f r i ddo = ( i ddo ( d ) + (0.5 10 ?3 ) c l v ddo ) (2 f ? f r ) + i ddo ( q ) f > 0.5 f r where: i ddi (d) , i ddo (d) are the input and output dynamic supply currents per channel (ma/mbps). c l is the output load capacitance (pf). v ddo is the output supply voltage (v). f is the input logic signal frequency (mhz); it is half of the input data rate expressed in units of mbps. f r is the input stage refresh rate (mbps). i ddi (q) , i ddo (q) are the specified input and output quiescent sup ply currents (ma).
ADUM3400/adum3401/adum3402 data sheet rev. b | page 22 of 24 to calculate the total i dd1 and i dd2 supply current, the supply currents for each input and output channel corresponding to v dd1 and v dd2 are calculated and totaled. figure 8 provides the per - channel input supply current as a function of the data rate. figure 9 and figure 10 provide the per - channel supply output cu r rent as a function of the data rate for an unloaded output condition and for a 15 pf output condition, respectively . figure 11 through figure 15 pr o vide the total v dd1 and v dd2 supply current as a function of the data rate for ADUM3400/adum3401/ adum3402 channel configurations. insulation lifetime all insulation structures eventually break down when subjected to voltage stress over a sufficiently long period. the rate of insulation degradation is depend e nt on the characteristics of the voltage waveform applied across the insulation. in addition to the testing performed by the regulatory agencies, analog devices ca r ries out an extensive set of evaluations to determine the lif e time of the insulation structure within the adum340x. a nalog devices performs accelerated life testing using voltage levels highe r than the rated continuous working voltage. acceleration factors for several operating conditions are determined. these factors allow calculation of the time to failure at the actual working voltage. the values shown in figure 21 summarize the peak voltage for 50 years of service life for a bipolar ac operating condition, and the maximum csa/vde approved working vol t ages. in many cases, the approved working voltage is higher than the 50- year service life voltage. o peration at these high working voltages can lead to shortened insulation life in some cases. the insulation lifetime of the adum340x depends on the voltage waveform type imposed across the isol a tion barrier. the i coupler insulation structure degrades at di fferent rates depending on whether the waveform is bipolar ac, unipolar ac, or dc. figure 21, figure 22 , and figure 23 illus trate these different isolation voltage wav e forms. bipolar ac voltage is the most stringent environment. the goal of a 50 - year operating lifetime under the ac bipolar condition determines the recommended maximum working voltage of analog devices . in the c ase of unipolar ac or dc voltage, the stress on the insulation is significantly lower , which allows operation at higher working voltages while still achieving a 50 - year service life. the working voltages listed in t able 10 can be applied while maintaining the 50 - year minimum lifetime provided the voltage conforms to either the unipolar ac or dc voltage cases. any cross insulation voltage waveform that does not conform to figu re 22 or figure 23 should be treated as a bipolar ac waveform and its peak volt age should be limited to the 50 - year lifetime voltage value listed in table 10 . note that th e voltage presented in figure 22 is shown as sinusoidal for illustration purposes only. it is meant to represent any voltage waveform varying between 0 v and some limiting value. the limiting value can be positive or negative, but the voltage cannot cross 0 v. 0v rated peak voltage 05985-021 figure 21 . bipolar ac waveform 0v rated peak voltage 05985-022 figure 22 . unipolar ac waveform 0v rated peak voltage 05985-023 figure 23 . dc waveform
data sheet ADUM3400/adum3401/adum3402 rev. b | page 23 of 24 outline dimensions controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design. compliant to jedec standards ms-013-aa 10.50 (0.4134) 10.10 (0.3976) 0.30 (0.0118) 0.10 (0.0039) 2.65 (0.1043) 2.35 (0.0925) 10.65 (0.4193) 10.00 (0.3937) 7.60 (0.2992) 7.40 (0.2913) 0.75 (0.0295) 0.25 (0.0098) 45 1.27 (0.0500) 0.40 (0.0157) coplanarity 0.10 0.33 (0.0130) 0.20 (0.0079) 0.51 (0.0201) 0.31 (0.0122) seating plane 8 0 16 9 8 1 1.27 (0.0500) bsc 03-27-2007-b figure 24 . 16 - lead standard small outline package [ soic_w ] wide body (rw - 16) dimension s shown in millimeters and (inches) ordering guide model 1 , 2 number of inputs, v dd1 side number of inputs, v dd2 side maximum data rate (mbps) maximum propagation delay, 5 v (ns) maximum pulse width distortion (ns) temperature range package description package option adum3 400arwz 4 0 1 100 40 ?40c to +105c 16- lead soic_w rw -16 adum3 400brwz 4 0 10 50 3 ?40c to +105c 16- lead soic_w rw -16 adum3 400crwz 4 0 90 32 2 ?40c to +105c 16- lead soic_w rw -16 adum3 401arwz 3 1 1 100 40 ?40c to +105c 16- lead soic_w rw -16 adum3 401brwz 3 1 10 50 3 ?40 c to +105c 16- lead soic_w rw -16 adum3 401crwz 3 1 90 32 2 ?40c to +105c 16- lead soic_w rw -16 adum3 402arwz 2 2 1 100 40 ?40c to +105c 16- lead soic_w rw -16 adum3 402brwz 2 2 10 50 3 ?40c to +105c 16- lead soic_w rw -16 adum3 402crwz 2 2 90 32 2 ?40c to +105c 16- lead soic_w rw -16 1 z = rohs compliant part. 2 tape and reel are available. the addition of an - rl suffix designates a 13 (1,000 units) tape - and - reel option.
ADUM3400/adum3401/adum3402 data sheet rev. b | page 24 of 24 notes ? 2006 C 2012 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d05985 -0- 2/12(b)

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